The present invention is directed to semiconductor packaging and, more particularly, to a semiconductor package with low tensile and thermal stresses.
One popular type of semiconductor package is a quad flat no-lead (QFN) package. A typical QFN package includes a lead frame formed by an array of external conductive leads and a die attach pad or flag. An integrated circuit (IC) or semiconductor die is attached to the die flag and electrically connected to the external conductive leads with bond wires. To secure the die to the die flag, an adhesive material typically is dispensed onto the exposed surface of the die flag, the die is then placed thereon, and the adhesive material is cured through exposure and/or heating for a specified time period. All of the components are then encapsulated by a mold compound to form the final QFN semiconductor package, which has a generally rigid structure.
The die flag of conventional QFN packages typically has a generally square or rectangular shape, and its entire surface is coated with the adhesive material in order to bond the entire inactive surface of the die to the flag. As such, in conventional QFN packages, the surface area of the bonding interface between the die, adhesive material and the die flag is relatively large.
However, due to the large surface area of the bonding interface and the rigid nature of the lead frame (particularly the die flag), a high bond or tensile stress is imposed on the die during the bonding process. This tensile stress, in turn, can result in cracking of the die during the bonding process.
Also, because of the large surface area of the bonding interface and the difference in the coefficients of thermal expansion (CTE) of the interface materials (i.e., the die, the adhesive material and the die flag), residual thermal stresses are developed at the bonding interface. Such thermal stresses can warp the semiconductor package, thus negatively affecting the temperature coefficient of offset (Tco) (i.e., the measure of non-pressure induced stresses, as a function of temperature, placed on the semiconductor package) and capability index (CpK) of the semiconductor package, and possibly leading to failure of the semiconductor device.
Chip-on-Lead (CoL) semiconductor packages are another conventional type of semiconductor package. In CoL packages, the die flag is removed and the die is mounted on extended leads using an adhesive. However, CoL semiconductor packages typically can only be used for larger sized dies because of the well known convention that the distance from the die edge to the lead tip should be no more than 50 micrometers. Also, because conventional CoL packages also include a bonding interface of a high surface area, they also suffer from tensile and residual thermal stresses at the bonding interfaces.
Accordingly, it would be advantageous to provide semiconductor packages that are useful for dies of all sizes and are not subjected to such high tensile and thermal stresses, and thus do not exhibit the defects that result from such stresses.